Hard Cover. New. New Book; Fast Shipping from UK; Not signed; Not First Edition; The The Interaction of Compilation Technology and Computer Architecture. ISBN 0792394518 9780792394518 [GB]

Springer , pp. 304 Index. Hardback. Used. Springer ISBN 0792394518 9780792394518 [US]

ISBN10: 0792394518, ISBN13: 9780792394518, [publisher: Springer] Hardcover
[Bayonne, NJ, U.S.A.] [Publication Year: 1994]
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ISBN10: 0792394518, ISBN13: 9780792394518, [publisher: Springer] Hardcover Ancien livre de bibliothèque. Petite(s) trace(s) de pliure sur la couverture. Edition 1994. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Very good. Former library book. Slightly creased cover. Edition 1994. Ammareal gives back up to 15% of this item's net price to charity organizations.
[Morangis, France] [Publication Year: 1994]

New York, NY Springer 1994 1994 ed. Hard cover New. C. Sewn binding. Cloth over boards. 285 p. Contains: Unspecified.

ISBN10: 0792394518, ISBN13: 9780792394518, [publisher: Springer] Hardcover
[Dallas, TX, U.S.A.] [Publication Year: 1994]

ISBN10: 0792394518, ISBN13: 9780792394518, [publisher: Springer] Hardcover pp. 304 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam
[Hounslow, United Kingdom] [Publication Year: 1994]

ISBN10: 0792394518, ISBN13: 9780792394518, [publisher: Springer US] Hardcover Druck auf Anfrage Neuware - Printed after ordering - In brief summary, the following results were presented in this work: - A linear time approach was developed to find register requirements for any specified CS schedule or filled MRT. - An algorithm was developed for finding register requirements for any kernel that has a dependence graph that is acyclic and has no data reuse on machines with depth independent instruction templates. - We presented an efficient method of estimating register requirements as a function of pipeline depth. - We developed a technique for efficiently finding bounds on register require ments as a function of pipeline depth. - Presented experimental data to verify these new techniques. - discussed some interesting design points for register file size on a number of different architectures. REFERENCES [1] Robert P. Colwell, Robert P. Nix, John J O'Donnell, David B Papworth, and Paul K. Rodman. A VLIW Architecture for a Trace Scheduling Com piler. In Architectural Support for Programming Languages and Operating Systems, pages 180-192, 1982. [2] C. Eisenbeis, W. Jalby, and A. Lichnewsky. Compile-Time Optimization of Memory and Register Usage on the Cray-2. In Proceedings of the Second Workshop on Languages and Compilers, Urbana l/inois, August 1989. [3] C. Eisenbeis, William Jalby, and Alain Lichnewsky. Squeezing More CPU Performance Out of a Cray-2 by Vector ...
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